1. Field of the Invention
The present invention relates to a semiconductor device to which a Wafer Level-Chip Size Package (WL-CSP) technology is applied.
2. Description of Related Arts
Recently, as semiconductor devices become increasingly more sophisticated and multifunctional, commercialization of Wafer Level-Chip Size Package (hereinafter referred to as WL-CSP) technology has progressed as well. With WL-CSP technology, the packaging process is completed at the wafer-level, and the size of an individual chip cut out by dicing reaches the size of the package.
A semiconductor device to which the WL-CSP technology is applied includes a semiconductor chip 82 with its surface covered by a surface protective film 81, a stress relaxation layer 83 laminated on the surface protective film 81 and a generally spherical solder ball 84 arranged on the stress relaxation layer 83, as shown in FIG. 8. The surface protective film 81 is formed with a pad opening 86 for exposing a part of internal wiring in the semiconductor chip 82 as an electrode pad 85. The stress relaxation layer 83 is formed with a through-hole 87 for exposing the electrode pad 85 exposed from the pad opening 86.
An under-bump layer 88 is formed so as to cover a surface of the electrode pad 85, an inner face of the through-hole 87 and a circumference of the through-hole 87 on the surface of the stress relaxation layer 83. The solder ball 84 is provided on a surface of the under-bump layer 88, and electrically connected with the electrode pad 85 via the solder ball 84. Mounting of the semiconductor device on a mounting board 89 (electrical and mechanical connection relative to the mounting board) is achieved by connecting the solder ball 84 to a pad 90 on the mounting board 89.
With the semiconductor device mounted on the mounting board 89, the solder ball 84 is sandwiched between the under-bump layer 88 on the semiconductor chip 82 and the pad 90 on the mounting board 89 to be firmly fixed thereon. In the relationship with the under-bump layer 88, however, the solder ball 84 contacts only the surface of the under-bump layer 88. As a result, there may have been a concern that when stress resulting from thermal expansion/contraction of the semiconductor chip 82 or the mounting board 89 is generated on the solder ball 84, the vicinity of a joint interface with the under-bump layer 88 of the solder ball 84 is cracked due to the stress. In addition, there may also have been a concern that the solder ball 84 is stripped off from the under-bump layer 88 due to the stress caused on the solder ball 84 since a contact area between the solder ball 84 and the under-bump layer 88 is small.
In particular, in a semiconductor device of a Land Grid Array (LGA) type, solder cannot be spread to soak over a side face of an under-bump layer since the volume of a solder ball (a solder pad) is small. As a result, a crack due to stress caused on the solder pad is easily generated. Further, it is difficult to obtain an adequate adhesive strength of the solder pad to the under-bump layer (a semiconductor chip).